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This update extends the functionality of clock control driver for the SAM D5x/E5x series. It introduces bindings for clock sources and generators, including DFLL, FDPLL, GCLK generator, MCLK CPU, OSC32K, RTC clock, and XOSC.
The driver now supports bootup clock initialization, asynchronous operation, and a set_rate API for dynamic clock management.
On the board side, the configuration has been updated to set the CPU clock to 120MHz using the FDPLL, sourced from the external XOSC
Add more functionality in clock control driver.
Add bindings for dfll, fdpll, gclk generator, mclk cpu, osc32k, rtc clock
and xosc.
Signed-off-by: Sunil Abraham <[email protected]>
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Add more functionality in clock control driver.
Implement bootup clock initialization, async on and set_rate API.
Signed-off-by: Sunil Abraham <[email protected]>
Configure CPU clock using FDPLL, sourced from XOSC to achieve 120Mhz.
Also configure UART clock to support bootup initialization.
Signed-off-by: Sunil Abraham <[email protected]>
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area: Boards/SoCs
platform: Microchip MEC
This update extends the functionality of clock control driver for the SAM D5x/E5x series. It introduces bindings for clock sources and generators, including DFLL, FDPLL, GCLK generator, MCLK CPU, OSC32K, RTC clock, and XOSC.
The driver now supports bootup clock initialization, asynchronous operation, and a set_rate API for dynamic clock management.
On the board side, the configuration has been updated to set the CPU clock to 120MHz using the FDPLL, sourced from the external XOSC